Note:
If Quartus freezes at roughly 10% completion during compilation, check the location of your project and VHDL files: storing files on a network drive (e.g., on the campus.mcgill.ca domain) instead of a local drive (e.g., C:\) will cause this issue.
# Overview
In this lab you will learn the basics of sequential logic. Specifically, you'll get hands-on experience working with:
- registers,
- counters, and
- VHDL components
Keep the practical aspects of these components in mind, and contrast them with the theoretical details that will be provided to you in class during the semester. Optionally, you can refer to Chapter 7 of your textbook for more details. For this lab, we will be implementing certain of these circuits in VHDL.
Concept Questions
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You may be asked questions of the following form at the end of the lab. You can find the answers in the textbook, manual or by Googling around the internet.
- What is a sequential circuit?
- Why do sequential circuits need a clock?
- What is a decoder?
- What is a register?
The goal of this lab is to finish the ping pong game implementation. We will need to reuse the decoders from the previous lab, as well as designing some additional sequential logic components. Once completed, your ping pong game will light up the on-board LEDs one at a time (mimicking the movement of your digital ping pong ball) and display the score of each player on the seven segment display.
Counters
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A sequential circuit has some memory and keeps track of time. When counting up (by one), we require a circuit capable of "remembering" the current count and adding 1 the next time we request a count. Such a counter also relies on a clock signal to know when time has passed and, so, when the current count needs to be stored. This will become more clear as we design the counter in VHDL.
Since the purpose of your counter is to light up a single LED at a time, from left to right then back again, you will need to count from 0 to 9 then back down to 0.
Score Keeper
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We will also create a circuit that behaves as follows: if the far left LED lights up, the right side player scores a point (and, similarly for the far right side LED, for the left side player). For this purpose, we will create a VHDL entity that takes as input the current position of the LED and the paddle button inputs. It will conditionally increase the score for the appropriate player if either of the above conditions are met. This score will then be displayed on a 7 segment display.
Clock Dividers
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Our game needs to run slow enough for humans to be able to play it. The built-in clocks on the FPGA board operate at a rate on the order of Megahertz. Flashing LEDs too quickly will make the game difficult, if not impossible, for any human to play. We can slow down the built-in clocks using a clock divider circuit. This circuit takes as input a (built-in) clock signal and slows it down to human response rates.
Components
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In the previous lab we connected all our entities using a Block Diagram File. Sometimes, you need to connect entities together programmatically using only VHDL. In this lab we will use the VHDL components abstraction to connect our building blocks together.
If you have a successful analysis of your top level entity then you can see the block diagram of this design by: clicking the _Tools_ menu item, followed by the _Netlist Viewers_ item, and then the _RTL Viewer_.
# Instructions
You should follow the video instructions below to build the circuits, before testing them and demoing to your TA:
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