Note:
If Quartus freezes at roughly 10% completion during compilation, check the location of your project and VHDL files: storing files on a network drive (e.g., on the campus.mcgill.ca domain) instead of a local drive (e.g., C:\) will cause this issue.
# Overview
This lab will use hands-on exercises to guide you through the basics of FPGAs and VHDL. Specifically, you will learn the basics of:
- the Quartus and Modelsim software tools,
- writing VHDL code,
- simulating and testing your HDL, and
- uploading and running your HDL configuration on the FPGA board.
During these exercises, you can refer to the course notes on Combinational Logic (and/or Chapter 6 in the textbook).
Concept Questions
-----------------
You may be asked some of these questions at the end of the lab. You can find the answers in the textbook, manual or using Google.
- What are the advantages of using an FPGA instead of a processor?
- What are the main components of a VHDL circuit design?
- Explain the functionality of **entity** and **architecture** in a VHDL design.
Your FPGA Board
--------------
You will be using the DE1-SOC board. You can find the manual for this board on the [DE1 Website](https://www.google.ca/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwjC6IWMl4jRAhUI4oMKHbh7DFkQFggbMAA&url=https%3A%2F%2Fwww.terasic.com.tw%2Fcgi-bin%2Fpage%2Farchive_download.pl%3FLanguage%3DTaiwan%26No%3D836%26FID%3Dfb723f964a1d785b94cd7880d8f210e5&usg=AFQjCNHft1kaYPj20BYA_pVENPwFgapzbQ&sig2=A59ZpskkS7i_rGdqPsQang&bvm=bv.142059868,d.amc). Take a moment to skim through the manual as you will be referring to it frequently during the labs.
Your FPGA board contains many different input and output devices, including buttons, switches and LEDs. At a high-level, the tasks we will assign to you throughout the coming labs will expose you to these different features on the FPGA, allowing you to manipulate different outputs sources and treat input from different sources, too.
The LED Decoder
-------------
This first lab experimen will focus on implementing two hardware decoders to control the behavior of the LEDs and the 7-segment display.
For the first (LED) decoder, it's useful to starting thinking of this decoder as a circuit. As such, we will provide you with its specification, now. The LED decoder has 4 inputs and 10 outputs. The inputs represent a number (encoded in binary) and the outputs are associated with an index for which LED should be lit (according to the inputs). We want to create a decoder that will light up the LED that corresponds to the (binary) number we've inputted. The truth table for this circuit is as follows:
Input | Output
------|-------
0000 | 1000000000
0001 | 0100000000
0010 | 0010000000
0011 | 0001000000
0100 | 0000100000
0101 | 0000010000
0110 | 0000001000
0111 | 0000000100
1000 | 0000000010
1001 | 0000000001
The 7-segment Decoder
---------------------
The 7-segment decoder will activate a 7-segment display in order to display a decimal number between 0 and 9 (inclusively). This circuit will similarly have 4 inputs, but now only 7 outputs: the input again correspond to a number (in binary) and the output ow corresponds to a output pattern for the display elements. Be sure to read the manual's description about the 7-segment display: it will give you more thorough insight on how to program the FPGA to light up the appropriate segements.
In other words, here (unlike with the LED decoder), _you_ will have to complete the spec before moving on to the synthesis of the circuit.
# Instructions
You will use your lab time to follow these video instructions in order to build two decoders and then demo them to your TA:
-